1. Field of the Invention
This invention relates to an interface circuit capable of performing a function test or a debugging operation on a semiconductor device, which has been shrunken for a high integration, and further relates to a method of testing and of debugging the semiconductor device using the interface circuit.
2. Description of the Related Art
A semiconductor device includes a microcomputer having a system-software. A function test of the semiconductor device or a debug for detecting and repairing an error of the software is performed by the following method. First, the semiconductor device, which has external terminals, is mounted on a printed board having pads. Then, test pins are contacted to the pads, each of which is connected electrically to one of the external terminals of the semiconductor device. However, since the number of external terminals is increased because of the high integration of the semiconductor device, it is necessary to increase the number of pads on the printed board. Therefore, it is necessary to secure the space for forming pads on the printed board. On the other hand, it is required to mount as many semiconductor devices on the printed board as possible. Thus, increasing the number of pads on the printed board conflicts with increasing the number of semiconductor devices on the printed board.
To avoid this issue, a new semiconductor device is developed. This new semiconductor device corresponds to JTAG (Joint Test Action Group), which was standardized by the IEEE in 1990 as “IEEE standard 1149.1-1990 Standard Access Port and Boundary-Scan Architecture”. The semiconductor device corresponding to JTAG includes a plurality of JTAG terminals. When the function test or the debug of the semiconductor device is performed, a test signal (test data) relating to a test logic, which is controlled by a host computer and a instruction signal (instruction data) relating to the debug are inputted to the semiconductor device via the JTAG terminals. After the function test or the debug is completed in the semiconductor device, a signal (data), which is a result of the function test or the debug, is outputted from the JTAG terminals. The number of JTAG terminals equals the number of kinds of JTAG signals, and a single kind of JTAG signal is inputted in or outputted from each JTAG terminal. The above-mentioned JTAG signals are inputted to or outputted from an internal circuit of the semiconductor device via a TAP (Test Access Port) controller of the semiconductor device or a variety of registers, which recognize the JTAG signals. The TAP controller controls the internal circuit of the semiconductor device in response to the JTAG signals.
However, the requirements for the high integration and downsizing are further intensified. It is not so easy to form interface signal terminals including JTAG terminals, the TAP controller for controlling the JTAG signals, and some circuits for the JTAG such as the registers in the high integrated and downsized semiconductor device. Thus, in the semiconductor device in the related art, the interface signal terminals including the JTAG terminals are located close to each other.
To avoid shorting out between the interface signal terminals, it is desired to reduce the number of JTAG terminals as possible.